PNN V4.2 · now with 4-bit and 1-bit weights
The new brain for today's AI
PNN is a next-generation neural core for large language models and AI systems. Every layer stays full rank but sparse, with no index stored — so models get smaller, run faster, and use less power.
Measured. Details and conditions on the benchmarks page.
What's new
From 32-bit floats to 1-bit weights
PNN V4.2 carries 4-bit weights through the whole stack — model file, CPU runtime and chip — and 1-bit PNN puts a vision transformer into 8.9 MB. INT8 stays the default.
- V4.2
4-bit weights, end to end
INT4 in the model file, the CPU runtime and the chip. A dual-mode multiplier computes one 8-bit or two 4-bit products per cycle, formally proven.
- 8.9 MB
1-bit PNN
ViT-B/16 at 71.19 % ImageNet top-1 with sign-only weights — 39× smaller than dense, 2.0× faster than dense int8 on a 4-core CPU.
- 4 CPUs
CPU runtime
Pre-built for x86-64 and ARM64. Faster than tuned dense int8 on Intel, AMD, Arm Neoverse and Apple M1, bit-exact — SLNG: single load, no gather.
- INT8
Quantised without retraining
PNN ViT-B/16 goes to INT8 for 0.32 points of top-1, 49 MB against 346 MB dense FP32. Published on Hugging Face.
- FPGA
Bit-exact on hardware
The generated 4-bit inference core runs on a Xilinx Artix-7: 24,000 outputs equal to the bit-exact model.
- 0.17×
Smaller silicon
Through sky130 place and route, a 1-bit processing element takes 0.17× the area and 0.07× the power of the 8-bit one; 4-bit takes 0.50× and 0.37×.
Offerings
Five ways to put PNN to work
From silicon to ready-made models: buy the chip, license the technology, have us optimize your model, run it on your CPUs, or pick one from the store.
- 01Ready-made models
Model store
Pre-converted PNN models, ready to deploy at the precision you need — starting with ViT-B/16 at FP32, BF16, INT8, INT4 and 1-bit.
Go in → - 02Service
Model inference
Run PNN models on available GPUs and CPUs, billed per hour — standard inference, or supermodel inference, distributed and fault-tolerant, for models of any size.
Run → - 03Service
Model optimization
We convert your network to PNN, recover its accuracy by distillation and quantise it to INT8, INT4 or 1-bit — delivered in the standard Hugging Face safetensors format.
Run → - 04Patent + know-how
IP licensing
License PNN for your own products: the patented connectivity, the encoder, CPU kernels and processing-element RTL. Evaluation licence first, then a production licence per design with a royalty per unit.
Talk to us → - 05Silicon
PNN chips
Inference chips that hold a whole model on-chip, from 8-bit down to 1-bit weights — for cameras, sensor heads and battery-powered devices — and training chips that learn in place.
Talk to us →
Key markets
Where the PNN chip goes
Datacenter
PNN LightStack — a 100-layer network in 100 nanoseconds
Ten PNN chiplets stacked in 3D and linked by light instead of copper: one layer per clock, weights held in silicon, no memory stalls at run time. Twelve stacks per liquid-cooled rack (concept, est).
Automotive
Perception at a fraction of the parameters
On real Waymo LiDAR, PNN matches the dense model to every printed digit with 6.7× fewer parameters — headroom for radar, LiDAR and camera stacks on automotive chips.
Robotics
Vision on board, within a robot's power budget
A 1-bit PNN vision transformer runs in 8.9 MB; a chip for it is modelled at 0.6 W — perception that stays on the robot (est).
Edge & IoT
Cameras, sensor heads, battery-powered devices
Whole models in on-chip memory, no DRAM for weights: a 12 mm² chip modelled to run ViT-B/16 ten times faster than a Jetson module (est).
Smartphones & PCs
Smaller models on the processors you already ship
PNN inference runs faster than dense int8 on Arm and x86 CPUs, and 4-bit and 1-bit weights cut the memory a model needs.
Industrial
Fixed models, long lifetimes, low power
A model fixed in silicon — the 1-bit processing element needs 0.17× the area and 0.07× the power of an 8-bit one, in place and route.
(est) = engineering estimate; the other figures are measured.
Datacenter · concept
PNN LightStack
An optical 3D processor stack for the PNN datacenter.
- One layer per nanosecond. Each layer is 65,536 (2¹⁶) neurons wide. A dense layer that size has 4.3 billion weights; PNN keeps about one in ten, structured, and every remaining connection is wired in silicon with its own multiplier. The whole layer computes at once, in a single cycle of a 1 GHz clock.
- A billion tokens per second. Every layer is a pipeline stage: while one token moves on to the next layer, the next token enters. A new token starts every nanosecond, so one stack processes 10⁹ tokens per second, across many requests in flight.
- A 430-billion-parameter model in 100 nanoseconds. 100 such layers — the size of a 430 B-parameter dense model, held as 43.5 B PNN weights — on ten chiplets of ten layers each.
- Linked by light. Chiplets talk over wavelength-multiplexed optical links instead of copper — under 0.5 pJ per bit, against 1.5–3 pJ for copper through-silicon vias.
- No memory stalls. Weights live in the silicon; high-bandwidth memory only preloads them at start-up.
- Rack scale. Twelve stacks per liquid-cooled rack: 12 billion tokens per second.
Architecture concept: throughput and latency are design targets, the other figures engineering estimates. Which number format reaches them at a given silicon area is under evaluation.
About us
A seasoned leadership team
We bring together the inventor of the technology, AI research, two company exits and standards-level reach across the industry — with a US presence where chips get designed — guided by a board of advisors from silicon IP, automotive, robotics, semiconductor analysis and IP law.
Dr. Jorg Nonnenmacher
CEO
Inventor of PNN. Founded, ran and sold two companies to Nasdaq-listed acquirers — the last of them AI that finds ads on TV.
Dr. Arnd Kohrs
Head of AI
PhD in prediction and collaborative filtering. Seasoned lead for customers and partners, from startups to industry heavyweights (IBM).
Thierry Fautier
Managing Director, US
Emmy Award winner for video AI. Former Chairman of the Ultra HD Forum, where he assembled the industry around a single format.
Isa Best, AI
VP Marketing
Our AI VP Marketing, based in San Francisco: leads PNN's marketing.
Board of advisors
Jos Burger
Chairman
Former CEO of Ultimaker, the Dutch 3D-printing company he led from 2015 to 2021. Earlier CEO of Palet Kabelcom. Chairs the supervisory board of E-magy.
Christophe Frey
Silicon IP
Former General Manager of Arm France, which grew fourfold under his lead. Joined Arm with its acquisition of SOISIC after 12 years at STMicroelectronics.
Erik Huggers
Robotics
Senior Advisor at EQT and board member of Hexagon, the industrial measurement and robotics group. Former CEO of Vevo; executive roles at Intel, Microsoft, BBC and Verizon.
Bruno Paucard
Automotive
Co-founder and former CEO of Silicon Mobility, maker of control chips for electric vehicles, acquired by Intel in 2024.
Amar Bouali
Formal verification
INRIA. Formerly CTO of Esterel Technologies, then at Ansys and Synopsys. Formal validation of system-on-chip and DSP designs; author of XEVE, the Esterel verification environment.
Tristan Gerra
Semiconductor analyst
Managing Director and Senior Analyst, Semiconductors, at Robert W. Baird since 2004, covering about 20 semiconductor companies. Earlier at SoundView and Prudential.
BlueshiftIP
IP counsel
Patent firm in Cambridge, Massachusetts, for software and computer technology. Co-founded by Robert Plotkin, an MIT-educated computer scientist and patent attorney.